1. Field of the Invention
The present invention relates to a failure memory device having a failure memory which is used in an apparatus for testing a semiconductor memory to store a failure (defect) data indicating that an output data from a memory under test does not accord with an expected value as a result of a logical comparison between them. More particularly, the present invention relates to a failure memory device which can store failure data in a failure memory in a form of compressed data and can use the data read out from the failure memory as a mask pattern for masking a logical comparison result.
2. Description of the Related Art
FIG. 3 shows a semiconductor memory testing apparatus which uses a prior art failure memory device. A timing signal, which is so-called clock signal, generated by a timing generator 11 is supplied to a pattern generator (PTN GEN) 12. Based on this timing signal, the pattern generator 12 generates address data, write data, control signals, etc. to supply them to a waveform shaping circuit (WAVE SHAPE CCT) 13. The waveform shaping circuit 13 converts the waveform of the inputted signal to a predetermined waveform having a predetermined level and supplies the signal to a memory under test (MUT) 14 at a predetermined timing.
The memory under test 14 has a plurality of cells each of which is specified by a supplied address data as a cell for writing data therein or reading out data therefrom, and data is written in or read out of the specified cell in accordance with a supplied control signal. Normally, after data is written in all the cells of the memory under test based on the address data and the control signal, the data is read out from each cell.
The data read out from the memory under test 14 is logically compared with an expected value data supplied from the pattern generator 12 bit by bit in a logical comparison circuit 15. When this logical comparison circuit 15 detects a mismatch between the readout data from the memory under test 14 and the expected value data from the pattern generator 12, the logical comparison circuit 15 determines that there is an error between them and outputs a defect data, so-called a failure data. A logic "1" is usually outputted as a failure data. On the other hand, when the readout data from the memory under test 14 matches with the expected value data from the pattern generator 12, the logical comparison circuit 15 determines that there is no error between them and outputs a defectless data, so-called a pass data. In this example, since the failure data is represented by logic "1", a logic "0" is outputted as a pass data. Naturally, the pass data (logic "0") is not stored in a failure memory (hereinafter also referred to as a fail memory) 17.
The failure output (logic "1") from the logical comparison circuit 15 is supplied to the failure memory 17 via a mask circuit 16 and stored therein. Usually, when a failure output is generated, a write signal is generated and writing of a failure data in the failure memory 17 is performed by the write signal applied to a write terminal WE of the fail memory 17. The mask circuit 16 has a mask pattern (a mask data for inhibiting a failure output from being written in the fail memory) read out from the failure memory 17 and supplied to the mask circuit 16 so that a failure output from the logical comparison circuit 15 can be selectively masked by the mask pattern on bit by bit basis. The mask pattern will be described later. In case any failure data is not written in the failure memory 17, each bit of a failure output passes through the mask circuit 16 as it is since no mask data exists. Incidentally, at the first test, since no failure data is written in the failure memory 17, the mask pattern does not contain any mask data. Therefore, each bit of a failure output passes through the mask circuit 16 as it is.
In a test of a semiconductor memory, since various tests are performed for a memory under test 14, a number of write and read operations are performed for each address. In general, a testing apparatus is arranged such that when a failure is detected for the first time in the data read out of an address, the failure data is written in the fail memory and thereafter, even if a failure is detected in the data read out of the same address in a succeeding read operation, the write operation of the failure data to that address is inhibited by the mask circuit 16 for masking the failure data so that the failure data can not be written in that address again. That is, the mask data (mask pattern) read out of the failure memory 17 serves to disable corresponding one or more AND gates of the mask circuit 16.
The failure memory 17 has the same capacity, i.e., the same address space and the same bit width, as that of the memory under test 14, and logic "1" representing a failure data is written in the address portion of the failure memory 17 which has the same address as that of the cell of the memory under test 14 which has been determined to be failure (defect). The failure information written in the failure memory 17 is used for the failure analysis, that is, the creation of a failure bit map for indicating which position in the memory under test 14 the failure exists, the repair process, i.e., the process for performing a relief of the failure bit using a relief redundant line provided in the memory under test 14, and the like. In such a way, when the failure data is written in the same address of the failure memory 17 as that of each cell of the memory under test 14 in correspondence to the address of each cell, it is necessary that as the capacity of the memory under test 14 increases, the capacity of the failure memory 17 must also be increased so as to have the same capacity as that of the memory under test 14, i.e., must have the increased memory capacity.
Incidentally, in the prior art semiconductor memory testing apparatus shown in FIG. 3, the memory under test 14 is a multi-bit memory in which a four bit data can be written at a time and a four bit data stored can be read out at a time. In case the memory under test 14 is a multi-bit memory of four bits, four exclusive-OR circuits corresponding to the respective output bits of the memory are provided in the logical comparison circuit 15, and four AND gates corresponding to the respective four exclusive-0R circuits are provided in the mask circuit 16. The outputs of the four AND gates are directly connected to the failure memory 17 except that one of the outputs is connected to the failure memory 17 via a multiplexer 19. The failure outputs from the AND gates are specified in address by a failure write address signal (address data for specifying an address of a cell in the failure memory 17 where a failure output is to be stored) from the pattern generator 12 and are written in the predetermined cells.
On the other hand, regarding the result of the comparison on these four bits, if there is a failure on any one or more of the four bits, the comparison result may be written in the failure memory 17 as the failure data of bits less than four bits, for example, of two bits or one bit. That is, the comparison result may be written in a form of bit compression or reduction. In the example shown in the figure, when the bit compression is performed, the outputs of the four AND gates of the mask circuit 16 are logically ORed by an OR circuit 18 and the ORed output is selected by the multiplexer 19 and is inputted to the failure memory 17 instead of the output of one AND gate of the mask circuit 16. In this case, a variable bit width memory is used as the failure memory 17, and a data indicating the degree of compression is inputted to an input terminal 20 of the failure memory 17. In this example, the four bit data is compressed to a one bit data. By this process, the written failure data has one bit width and the depth of four time.
In the aforementioned multi-bit memory for writing and reading a plurality of bits in and out of one address at a time, a relief redundant line for relieving a failure bit detected is often provided for every plurality of bits. For example, in a multi-bit memory of 16 bits, a common redundant relief line is often provided for each of upper 8 bits and lower 8 bits or for each of 8 even bits and 8 odd bits. In such a case, when the failure memory 17 is used for the repair process, respective logical comparison results for a plurality of data bits read out from the multi-bit memory under test 14 are logically ORed by the OR circuit 18 and then the ORed output is taken in the failure memory 17 as mentioned above. In other word, failure data are compressed and then the compressed data is taken in the failure memory 17. By such a process, the capacity of the failure memory 17 is not necessary to be equal to the capacity of the memory under test 14 and thus, the capacity of the failure memory 17 can be reduced less than that of the memory under test 14.
As mentioned above, a semiconductor memory is generally subjected to various tests by changing parameters, and the portion where a failure data is already stored once is masked by a mask data so that a failure data detected in a succeeding test is not stored therein again. To this end, two areas (blocks), one for storing the failure data and the other for generating the mask data, are provided in the failure memory. A storing process of the failure data and a process of generating the mask data in this case will be explained with reference to the flow chart of FIG. 4.
First, the first test is performed in step S1. If the test result is "pass", i.e., defectless, then the process proceeds to the next test in step S4. If the test result is "failure", i.e., defect, then a failure data is taken in block 1 of the failure memory. Next, a repair analysis is performed on the failure data taken in the block 1 in step S2, and if the failure produced can be relieved, then the process proceeds to step S3 and if the failure produced cannot be relieved, then the process ends. In step S3, a copy of the failure data taken in the block 1 is formed and stored in block 2 for pattern generation, and thereafter the block 1 is cleared. In the second test and the succeeding tests in step 4, the failure data of the test result (i.e., the logical comparison result) is taken in the block 1 of the failure memory while a mask pattern is being generated from the block 2. This mask pattern serves not to always write in the failure memory the logical comparison result on a cell of the memory under test where a failure data has occurred in the previous test. Similarly to the first test, when this test result is "pass", the process proceeds to the next test in step S4, and when this test result is "failure", the process proceeds to step S5. In step S5, corresponding bits in the data stored in the block 1 and the data stored in the block 2 are logically ORed and this ORed data is written in the block i. In step S6, a repair analysis is performed on the ORed data and a check is effected to determine whether the "failure" produced in the previous tests can be relieved. If the "failure" can be relieved, the process proceeds to step S7 wherein a copy of the failure data written in the block 1 is taken and is stored in the block 2 for the mask pattern, and thereafter the failure data in the block 1 is cleared. On the other hand, if the "failure" cannot be relieved, the process ends. The above process is repeated for the number of times equal to the number of test items.
In the prior art failure memory device of the aforementioned arrangement, when the failure data is written in each cell of the failure memory in correspondence to each cell (bit) of the memory under test, the mask pattern can be generated. However, when a plurality of logical comparison results are logically ORed and the ORed data in the form of data compression is written in the failure memory, the corresponding mask pattern cannot be generated.